During the fabrication of integrated circuits such as memory devices, it is conventional to test such memory devices at several stages during the fabrication process. For example, memory devices are normally connected to a tester with a probe card when the memory devices are still in wafer form. In a final test occurring after the memory devices have been diced from the wafer and packaged, the memory devices are placed into sockets on a load board. The load board is then placed on a test head, typically by a robotic handler. The test head makes electrical contact with conductors on the load board that are connected to the memory devices. The test head is connected through a cable to a high-speed tester so that the tester can apply signals to and receive signals from the memory devices.
While the above-described testing environment works well in many applications, it is not without its limitations and disadvantages. One problem is the difficulty in testing various timing characteristics of memory devices, particularly at the high operating speeds for which such integrated circuits are designed. This difficulty is exacerbated by the relatively long cables that are used to connect the tester to the test head on which a load board containing the memory devices is mounted. However, it has been possible to overcome these difficulties by using complex, and hence very expensive, memory device testers that are able to independently control the assertion time and duration of each of the digital signals applied to the memory devices. A large number of testers are normally required for a high capacity fabrication plant, thus greatly increasing the cost of the plant and the manufacturing expense of memory devices.
One improved testing system that has been proposed is to fabricate an integrated test circuit that performs most if not all of the functions of conventional testers, and mount the integrated test circuit on the test head or load board containing the memory devices being tested. By placing the testing function on the test head or load board itself, the problems inherent in coupling test signals between a testing system and a test head are eliminated. Furthermore, since even custom integrated circuits can be fabricated relatively inexpensively, the cost of testing systems can be greatly reduced.
One difficulty in providing an integrated test circuit having the capability to test memory devices in this manner stems from the difficulty in accurately testing the ability of a memory device to operate correctly as the timing at which memory device signals, such as command and address signals and clock enable signals, are asserted is varied and the duration that such signals are asserted is varied. The timing and duration of these signals could be precisely varied if, like conventional testers, the integrated test circuit was able to independently control the assertion time and duration of each of the digital signals applied to the memory devices. However, it is presently not possible for an integrated test circuit to incorporate the level of complexity that would be required for it to operate in this manner.
Attempts have been made to provide a relatively simple testing system that precisely controls the assertion time and duration of digital signals applied to memory devices. One example of a conventional testing system 10 of this type is shown in FIG. 1. The testing system 10 includes a test signal generator 14 that stores and sequentially outputs sets of signals corresponding to memory commands and addresses. Each set of signals includes the same number of signals that are in a command or address applied to a memory device being tested. The test signal generator 14 may be implemented, for example, using a memory array operated by a microcontroller. The test signal generator 14 includes two output ports 16, 18 from which sets of tests signals corresponding to two commands or addresses are alternately transmitted. The signals are stored in the test signal generator 14 so that the logic levels of signals S1 from the port 16 will be the valid command or address signals that are to be applied to a memory device being tested. The signals S2 output from the port 18 are chosen to be either the compliment of the S1 signals or the same as the S1 signals depending on the operating mode of the testing system 10. The output ports 16, 18 are coupled through respective buses 22, 24 to respective signal input ports I1, I2 of a plurality of two-phase transmitters 20. Although only one phase transmitter 20 is shown for purposes of clarity, in actuality, one transmitter 20 is provided for each bit of a command and/or address for which a signal is to be output from the testing system 10. Each transmitter 20 also includes two clock ports C1, C2 and an output port Q.
In operation, the first signal input port I1, is connected to the output port Q responsive to a rising edge of a clock signal CLK1 applied to the C1 port. Similarly, the second signal input port I2 is connected to the output port Q responsive to a rising edge of a clock signal CLK2 applied to the C2 port. As a result, the S1 signal is coupled to the output port Q at the rising edge of the CLK1 signal and is isolated from the output port Q at the rising edge of the CLK2 signal. Similarly, the S2 signal is coupled to the output port Q at the rising edge of the CLK2 signal and is isolated from the output port Q at the rising edge of the CLK1 signal. Insofar as each of the valid command and address signals correspond to a respective one of the S1 signals, the command or address signals start at the rising edge of the CLK1 signal and terminate at the rising edge of the CLK2 signal.
The clock signals CLK1 and CLK2 are generated at the output of a clock delay circuit 30, which receives an input clock signal CLKIN. The clock delay circuit 30 includes two clock signal paths 34, 38, which generate the clock signals CLK1 and CLK2, respectively. The first signal path 34 includes a phase interpolator 40 and a clock distribution tree 44, which distributes the output of the interpolator 40 to respective transmitters 20 (it being remembered that a transmitter 20 is provided for each signal output from the testing system 10). As is well-known in the art, a phase interpolator produces a delayed signal from an input signal by interpolating between the phase of two input signals by a precisely controlled amount. The phase interpolator 40 receives the CLKIN signal and its complementCLKIN*. The degree of precision of the delay of a signal generated by a phase interpolator depends on the precision of the input signal frequency. The phase interpolator 40 can, for example, interpolate between the phases of the CLKIN and CLKIN* signals in 100 increments. If the CLKIN and CLKIN* signals have a frequency of 5 mHz, the delay of the CLK1 signal can then be adjusted in 1 nanosecond increments. Each of the branches in the clock distribution tree 44 that receive the clock signal from the interpolator 40 includes a delay line 48 from which a respective CLK1 signal is generated. The delays of the delay lines 48 are adjusted so that the signals corresponding to all bits of a command or address are applied to a memory device being tested at the same time. The delay lines 48 thus correct for bit-to-bit timing errors. Alternatively, the delays of the delay lines 48 may be adjusted so that the signals corresponding to groups of a command or address are applied to a memory device being tested at the same time.
The second clock signal path 38 is identical to the first clock signal path 26, and it therefore also includes a phase interpolator 50, clock distribution tree 54 and delay line 58.
Finally, the system 10 also includes a control circuit 60 for controlling the phase shift of the phase interpolator 40 and the respective delays provided by the delay lines 48, 58.
All of the command signals are sometimes referred to as a pin group, and all of the address signals are referred to as a different pin group. It is desirable for the assertion time and duration of the signals in the command pin group to be controlled independently of the control of the assertion time and duration of the signals in the address pin group. Therefore, one of the testing systems 10 is generally provided for the signals in the command pin group, and another of the testing systems 10 is provided for the signals in the address pin group. It is also possible to provide a testing system 10 for each of a large number of subsets of the pin groups.
The operation of the testing system 10 shown in FIG. 1 will now be explained with reference to the timing diagram shown in FIG. 2. The testing system 10 attempts to test the operation of a memory device by applying sets of command or address signals to the memory device that have an adjustable start time and an adjustable duration. As explained above, the command or address signals correspond to the S1 signals, and the S2 signals are either the same as or the compliment of the valid command or address signals.
The CLKIN signal applied to the inputs of the phase interpolators 40, 50 is shown in FIG. 2 along with the command or address signals CAE1-CAE6 output from the port 16 and the command or address signals CAO1-CAO6 output from the port 18. Two examples are shown in FIG. 2, namely an “A” example and a “B” example. In the “A” example, the phase interpolator 40 and the delay line 48 in the respective branch delay the CLKIN signal about one-quarter of the period of the CLKIN signal to produce the C1A signal. However, the phase interpolator 50 and the delay line 58 in the respective branch delay the CLKIN signal by a substantially greater amount to produce the C2A signal, which is delayed from the CLKIN signal by about an entire period of the CLKIN signal. As a result the QA signals at the output of the transmitters 20 are equal to the CAE1 signals responsive to the rising edge of the C1A signal at time t1, and they are equal to the CAO1 signals (which are the compliment of the CAE1 signals) responsive to the rising edge of the C2A signal at time t4. The CAE signals simulating a valid command or address thus have a duration that is almost as long as the period of the CLKIN signal. However, since the C1A signal is delayed by about one-quarter period of the CLKIN signal, the command or address does not become active until one-quarter period after the rising edge of the CLKIN signal. Therefore, in the “A” example, the delays of the phase interpolators 40, 50 and the delay lines 48, 58 are chosen so that the valid period of the command or address starts one-quarter period late and has a duration that is three-quarters of the maximum possible duration.
In the “B” example, the C1B signal is delayed from the CLKIN signal by half the period of the CLKIN signal, and the C2B signal is delayed from the CLKIN signal by three-quarters of the period of the CLKIN signal. As a result, the valid period of the command or address starts one-half period after the rising edge of the CLKIN signal, and it has a duration that is one-quarter of the maximum possible duration. By properly choosing the delays of the phase interpolators 40, 50 and the delay lines 48, 58, the commands and addresses can be applied to a memory device under test with any desired assertion time and duration.
Although the testing system 10 shown in FIG. 1 is able to output command and address signals with any desired assertion time and duration, it is still undesirably complex and it consumes a substantial amount of power, particularly since one of the transmitters 20 must be provided for each of a large number of command and address bits. Further, the need for two phase interpolators 40, 50 results in undesirable complexity and power consumption because conventional phase interpolators are complex and they consume a great deal of power. As a result, it may be impractical to incorporate the testing system 10 in an integrated test circuit.
There is therefore a need for a relatively simple testing system and method that is capable of precisely varying the assertion time and duration of memory devices signals, such as command signals, address signals and clock enable signals. A relatively simple testing system having these capabilities would make it highly practical to incorporate the system in an integrated test circuit that could be mounted on a load board or test head. Additionally, the system would make it possible to greatly reduce the cost of conventional memory device testers.